High NA EUV Progress Signals Intel Manufacturing Momentum as ASML and TSMC Advance Adoption

Intel Puts High NA EUV Into Production as the Industry Prepares to Follow

Intel (INTC) and ASML (ASML) highlighted progress bringing next-generation High Numerical Aperture Extreme Ultraviolet lithography, or High NA EUV, into semiconductor manufacturing. More than one million wafers have now been processed across tool testing, research and development, and production, including select layers of Intel's Panther Lake processors.

The announcement put Intel's current deployment alongside longer-term adoption plans from Taiwan Semiconductor Manufacturing (TSM). TSMC plans to introduce High NA EUV into advanced-node, high-volume manufacturing beginning in 2030 and expects its use to expand as AI-driven transistor architectures become more complex.

Key Points

• Intel Foundry and ASML have processed more than one million wafers using High NA EUV, including select production layers of Intel Core Ultra Series 3 Panther Lake processors.
• Intel said High NA equipment is meeting expectations for overlay, throughput and availability, while Intel 18A layers using the technology meet or exceed comparable layers produced with existing EUV equipment.
• TSMC plans to introduce High NA EUV into advanced-node volume manufacturing in 2030, with greater use expected as AI-related chip architectures become more complex.

Intel Moves High NA EUV Beyond the Development Stage

High NA EUV is a next-generation lithography technology from ASML designed to help semiconductor manufacturers print smaller and more complex features onto wafers. The latest Intel-ASML update is significant because the technology is already being used in Intel's high-volume manufacturing rather than remaining limited to research and testing.

Intel Foundry said more than one million wafers have been processed using High NA EUV across early tool certification and testing, research and development, and volume production. Selected layers of Intel Core Ultra Series 3 processors, code-named Panther Lake, are already being manufactured with the technology.

Intel said overlay, throughput and equipment availability are meeting its expectations. Overlay refers to how accurately successive patterns are aligned on a wafer, while throughput measures how efficiently wafers move through the manufacturing process.

The company also reported that products manufactured on Intel 18A using High NA for selected layers continue to deliver performance that meets or exceeds comparable layers patterned using ASML's existing 0.33 numerical-aperture EUV platform.

ASML CEO Christophe Fouquet described Intel Foundry as one of the industry's key leaders in adopting High NA, pointing to its installation of the first commercial EXE system in 2024, qualification of newer equipment and shipment of the first high-volume logic product manufactured using the technology.

The progress coincided with a strong move in INTC stock. Intel shares were up more than 8% in Tuesday trading after also gaining more than 4% in the previous session. The supplied market data showed ASML shares gaining nearly 3%.

Why Does High NA EUV Matter for Intel and ASML?

Intel and ASML are working on both immediate manufacturing applications and the infrastructure needed for broader future adoption.

For current production, Intel Foundry says customers can use High NA with today's standard 6-inch mask format. That can be accomplished either by designing within the available mask area or through Intel's reticle-stitching technology and process design kit solutions.

Reticle stitching allows different exposures to be combined, enabling chipmakers to use High NA EUV without waiting for a larger mask standard.

At the same time, Intel Foundry has spent more than three years supporting development of a larger 6-by-12-inch mask format. Intel and ASML are working with mask makers, automation suppliers, electronic design automation partners, materials companies and other semiconductor manufacturers to develop the standards and infrastructure required for that transition.

The larger format is intended to support future High NA scaling. Intel and ASML are therefore pursuing two paths simultaneously: making the technology usable with existing masks today while helping prepare the semiconductor ecosystem for larger masks in the future.

For ASML, the industry adoption schedule extends beyond Intel. Samsung plans to introduce High NA EUV into high-volume DRAM manufacturing by 2028, while TSMC plans to begin using the technology in advanced-node high-volume manufacturing in 2030.

What Does TSMC's Adoption Timeline Signal?

TSMC's planned 2030 introduction places High NA EUV within its future advanced-node manufacturing roadmap even though Intel is already using the technology in volume production.

The supplied information says TSMC expects the number of High NA layers to increase over time as transistor architectures become more complicated, particularly for AI applications.

That places the technology within a broader semiconductor manufacturing challenge. Increasingly complex chips require manufacturers to produce smaller and more intricate patterns while maintaining the accuracy and production efficiency needed for high-volume manufacturing.

TSMC is also participating in work on larger mask formats. ASML and TSMC are targeting a pilot line for larger masks by 2031, with the technology expected to be ready for advanced-node production by 2033.

Until that infrastructure is available, Intel and ASML's work with existing 6-inch masks and reticle stitching provides a path for High NA deployment under the industry's current manufacturing framework.

Tuesday's stock market reaction reflected interest across the semiconductor manufacturing chain. Intel shares gained more than 8%, ASML approached a 3% advance and TSM shares rose more than 2% in the supplied market data.

What It Means for Investors

The High NA announcement provides a measurable manufacturing milestone: more than one million wafers have passed through the technology across certification, development and production, and Intel is already using it on selected Panther Lake layers.

For Intel, the focus now extends beyond gaining access to advanced lithography equipment. The company has demonstrated that High NA can operate within volume manufacturing while meeting its expectations for overlay, throughput and availability.

For ASML, the adoption schedules described by Intel, Samsung and TSMC illustrate how High NA could move through different parts of semiconductor manufacturing over the coming years. Intel is already using the technology, Samsung plans high-volume DRAM adoption in 2028 and TSMC plans advanced-node deployment beginning in 2030.

TSMC's timeline also shows that adoption will not occur simultaneously across the industry. Different manufacturers are introducing High NA according to their own production schedules and applications.

The next phase will involve both expanding High NA's role in manufacturing and continuing development of the supporting mask ecosystem. Intel and ASML are working on near-term use with current 6-inch masks while the broader industry prepares for larger-format masks intended to support future scaling.

Conclusion

Intel and ASML's latest High NA EUV update moves the semiconductor story from technological potential toward measurable manufacturing deployment.

More than one million wafers have been processed, selected Panther Lake layers are already being manufactured with High NA, and Intel says key production measures are meeting expectations. Intel 18A layers produced with the technology are also meeting or exceeding the performance of comparable layers patterned using the existing EUV platform.

The broader adoption timeline extends well beyond Intel. Samsung plans to introduce High NA into high-volume DRAM manufacturing in 2028, while TSMC expects to begin advanced-node volume manufacturing with the technology in 2030.

Together, those milestones establish a multiyear adoption path for ASML's next-generation lithography technology as semiconductor manufacturers prepare for increasingly complex chip designs.

FAQs

What is High NA EUV?

High NA EUV is a next-generation lithography technology from ASML that helps semiconductor manufacturers print smaller and more complex features onto semiconductor wafers.

Is Intel already using High NA EUV in production?

Yes. Intel Foundry is using High NA EUV in high-volume manufacturing on select layers of Intel Core Ultra Series 3 processors, code-named Panther Lake. More than one million wafers have been processed across testing, development and production.

How is Intel's High NA EUV equipment performing?

Intel said overlay, throughput and availability are meeting its expectations. It also said Intel 18A products using High NA on selected layers meet or exceed the performance of comparable layers patterned using ASML's existing EUV platform.

When does TSMC plan to use High NA EUV?

TSMC plans to use High NA EUV in advanced-node, high-volume manufacturing beginning in 2030 and expects the number of High NA layers to increase as AI-driven transistor architectures become more complex.

Why are Intel and ASML working on larger masks?

Intel Foundry and ASML are working with the semiconductor ecosystem to develop larger-format masks and supporting infrastructure for future High NA scaling, while also enabling manufacturers to use High NA with today's standard 6-inch masks.

This article was created with AI assistance and reviewed by an editor. For details, please refer to our Terms of Use.

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